1. Field of the Invention
This invention relates to a circuit for generating an output signal having a timing cycle of predetermined duration, the timing cycle having first and second portions separated by an interruption. The duration of the second portion is equal to the predetermined duration of the timing cycle less the duration of the first portion.
2. Description of the Prior Art
My copending application entitled "Digital Delay Generator" describes the use of interruptable signal generating circuitry in order to virtually eliminate the timing jitter normally associated with digital delay generator systems and to obtain delay times in such systems over both integer and non-integer multiples of the time interval between clocked timing pulses. In attempting to locate an interruptable signal generator for use in that application, it was determined that devices such as the present invention were unavailable. Consequently, the present invention was conceived and reduced to practice as part of the efforts associated with the invention discussed in the above mentioned copending application.